Faculty member proposing: Dave Poplawski

Email address: pop@mtu.edu

Course syllabus:   

	Knowledge Superscalar Architectures  Exposure    VLIW Architecture    Compiler instruction scheduling Familiarity    Some current real machines Mastery    Instruction fetch/decode    Instruction issue    Register renaming    Load/store ordering    Exception recovery		Skills  Superscalar Architectures  Exposure    Simulation Techniques Familiarity    Trace-Driven Simulation    Statistical analysis of results Mastery    Generating Program Traces    Using traces to generate performance statistics
	Multiprocessor Performance Models  Exposure    Simple applied queueing theory    Simple applied markov modeling Familiarity    Analytic performance modeling Mastery    Interconnect bandwidth models    System performance models		Multiprocessor Performance Models  Exposure    none Familiarity    Construct markov and queueing models Mastery    Construct and analyze bandwith and performance models
	Multiprocessor Cache/Memory Coherency/Consistency  Exposure    Memory consistency models (strong, weak, release) Familiarity    Cache/memory coherency issues Mastery    Several snooping protocols    One complex directory-based protocol    Tradeoffs between various protocols		Multiprocessor Cache/Memory Coherency/Consistency  Exposure    none Familiarity    none Mastery    none