FAST: Flexible Architecture Simulation Tool
Soner Onder, Michigan Technological University
Rajiv Gupta, The University of Arizona
Description
FAST is a sophisticated tool which is currently over 34,000 lines of C++
code. Both the instruction set and the microarchitecture are specified
using an architecture description language (ADL) developed by us. The typical
descriptions of superscalar processors written in ADL range from 6,000
to 8,000 lines and the generated simulators consist of 30,000 to 35,000
lines of C++ code. This system has been functional for over a year during
which time simulators for numerous superscalar configurations have been
successfully built. Generating a new simulator using this system takes
between 1 and 3 man months. In contrast handcoded simulators typically
take 12 to 18 man months to develop. One reason for increased productivity
is FAST's debugging environment. The simulation speeds of the generated
simulators range from 150,000 to 200,000 simulation cycles per second depending
upon the complexity of the superscalar design which is quite competetive
with handcoded simulators. FAST also provides extensive support for performance
data collection. The increased productivity not only allows simulators
to be developed quickly, but more importantly, it enables thorough exploration
of the design space that otherwise would not be possible.
This system is being extended to allow exploration of the design space
of power-adaptive microarchitectures. The ADL language is being extended
so that the next generation of the FAST system will provide power consumption
estimates.
For more details see: