My main area of interest is in the hardware aspects of Instruction Level Parallelism (ILP). I am especially interested in branch prediction and speculative execution, and in how to supply enough register/memory bandwidth to support high levels of parallelism. This later interest translates into memory hierarchy issues, such as caches, local memory, etc. Since compilers are so intimately involved in achieving good parallelism, I am peripherally interested in code generation and optimization, especially instruction scheduling.

I also have less focussed interests in parallel computer architectures in general, including MIMD machines of both the shared and distributed memory orientation.