Publications


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JOURNAL PUBLICATIONS

  1. S. Carr and P. Sweany. "An Experimental Evaluation of Scalar Replacement on Scientific Benchmarks", Software - Practice & Experience 33(15), December 2003.
  2. S. Carr, J. Mayo and C.-K. Shene. "ThreadMentor: A Pedagogical Tool for Multithreaded Programming", ACM Journal of Educational Resources in Computing 3(1), March 2003.
  3. S. Carr, J. Mayo and C.-K. Shene. Race Conditions: A Case Study, The Journal of Computing in Small Colleges 17(1), September 2001.
  4. P. Sweany, S. Carr and B.L. Huber, ``Global Instruction Scheduling Without Copies'',Digital Technical Journal 10(1), December 1998.
  5. C.-K. Shene and S. Carr. ``The Design of a Multithreaded Programming Course and Its Accompanying Software Tools'', The Journal of Computing in Small Colleges 14(1), November 1998.
  6. S. Carr and R.B. Lehoucq, ``Compiler Blockability of Dense Matrix Factorizations'', ACM Transactions on Mathematical Software 23(3), September 1997.
  7. K. McKinley, S. Carr and C.-W. Tseng, ``Improving Data Locality with Loop Transformations'', ACM Transactions on Programming Languages and Systems 18(4), July 1996.
  8. S. Carr and K. Kennedy, ``Improving the Ratio of Memory Operations to Floating-Point Operations in Loops'', ACM Transactions on Programming Languages and Systems 16(6), November 1994.
  9. S. Carr and K. Kennedy, ``Scalar Replacement in the Presence of Conditional Control Flow'', Software - Practice & Experience 24(1), January 1994.

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CONFERENCE AND WORKSHOP PUBLICATIONS
  1. Y. Ma and S. Carr. "Register Pressure Guided Unroll-and-Jam", In The 2008 Open64 Workshop, April 6, 2008.
  2. C. Fang, S. Carr, S. Onder and Z. Wang. "Feedback-directed Memory Disambiguation Through Store Distance Analysis", In Proceedings of the 20th ACM International Conference on Supercomputing, Queensland, Australia, June 2006.
  3. C. Fang, S. Carr, S. Onder and Z. Wang. "Path-based Reuse Distance Analysis", In Proceedings of the 15th International Conference on Compiler Construction, Vienna, Austria, March 2006.
  4. C. Fang, S. Carr, S. Onder and Z. Wang. "Instruction Based Memory Distance Analysis and Its Application to Optimization", In Proceedings of the Fourteenth ACM/IEEE International Conference on Parallel Architectures and Compilation Techniques, St. Louis, MO, September 2005.
  5. P. Zhou, S. Onder and S. Carr. "Fast Branch Misprediction Recovery in Out-of-order Superscalar Processors", In Proceedings of the 2005 ACM International Conference on Supercomputing, Boston, MA, June 2005.
  6. S. Carr and S. Onder. "A Case for a Working-set-based Memory Hierarchy", In Proceedings of the 2005 ACM International Conference on Computing Frontiers, Ischia, Italy, May 2005.
  7. S. Carr and P. Sweany. "Automatic Data Partitioning for the Agere Payload Plus Network Processor", In Proceedings of the ACM/IEEE 2004 International Conference on Compilers, Architecture and Synthesis for Embedded Systems, Washington, D.C., September 2004.
  8. Y. Ma, S. Carr and R. Ge. "Low-cost Register-pressure Prediction for Scalar Replacement using Pseudo-schedules", In Proceedings of the 2004 Interational Conference on Parallel Processing, Montreal, Canada, August 15-18, 2004.
  9. C. Fang, S. Carr, S. Onder and Z. Wang. "Reuse-distance-based Miss-rate Prediction on a Per Instruction Basis", In Proceedings of the 2004 ACM Workshop on Memory System Performance, Washington, D.C., June 2004.
  10. D. Callahan, S. Carr and K. Kennedy. " Retrospective: Improving Register Allocation for Subscripted Variables", In 20 Years of the ACM SIGPLAN Conference on Programming Language Design and Implementation (1979 - 1999): A Selection, Kathryn S. McKinley, Editor, ACM SIGPLAN Notices, Volume 39, Number 4, April 2004.
  11. S. Carr, C. Fang, T. Jozwowski, J. Mayo and C.-K. Shene. "ConcurrentMentor: A Visualization System for Distributed Programming Education", In Proceedings of the 2003 International Conference on Parallel and Distributed Processing Techniques and Applications, Las Vegas, NV, June 23-26, 2003.
  12. P. Sweany and S. Carr. "Building a C Compiler Retargetable for DSP Processors", In The 1st Workshop on Optimizations for DSP and Embedded Systems (ODES), San Francisco, California, March 2003.
  13. Y. Qian, S. Carr and P. Sweany. "Optimizing Loop Performance for Clustered VLIW Architectures", In Proceedings of the Eleventh IEEE International Conference on Parallel Architectures and Compiler Techniques (PACT-2002), Charlottesville, Virginia, September 22-25, 2002.
  14. Y. Qian, S. Carr and P. Sweany. "Loop Fusion for Clustered VLIW Architectures", In Proceedings of the ACM 2002 Joint Conference on Languages, Compilers and Tools for Embedded Systems and Software and Compilers for Embedded Systems, Berlin, Germany, June 19-21, 2002.
  15. S. Carr, P. Chen, T. Jozwowski, J. Mayo and C.-K. Shene. "Channels, Visualization and Topology Editor", In Proceedings of the Seventh Annual ACM SIGCSE Conference on Innovation and Technology in Computer Science Education, Aarhus, Denmark, June 24-26, 2002.
  16. D. Sule, S. Carr, and P. Sweany. "Evaluating Register Partitioning with Genetic Algorithms", In Proceedings of the Fourth International Conference on Massively Parallel Computing Systems, Ischia, Italy, April 2002.
  17. S. Carr. C.Fang, T. Jozwowski, J. Mayo and C.-K. Shene. "A Communication Library to Support Concurrent Programming Courses", In Proceedings of the 33rd ACM SIGCSE Technical Symposium on Computer Sceince Education, Northern Kentucky, February 2002.
  18. X. Huang, S. Carr and P. Sweany. "Loop Transformations for Architectures with Partitioned Register Banks", In Proceedings of the 2001 ACM Workshop on Languages, Compilers and Tools for Embedded Systems (LCTES '2001), Snowbird, Utah, June 22-23, 2001.
  19. M. Bedy, S. Carr, S. Onder and P. Sweany. "Improving Software Pipelining by Hiding Memory Latency with Combined Loads and Prefetches", In Interaction between Compilers and Computer Architectures, G. Lee and P.-C. Yew ed., Kluwer Academic Publishers, 2001.
  20. J. Hiser, S. Carr and P. Sweany. "Global Register Partitioning", In Proceedings of the 2000 IEEE International Conference on Parallel Architectures and Compiler Techniques, Philadelphia, PA, October 15-19, 2000.
  21. S. Carr and C.-K. Shene. ``A Portable Class Library for Teaching Multithreaded Programming''. In Proceedings of the Fifth ACM SIGCSE Annual Conference on Innovation and Technology in Computer Science Education, Helsinki, Finland, July 11-13, 2000.
  22. J. Hiser, S. Carr, P. Sweany, and S.J. Beaty. ``Register Assignment for Software Pipelining with Partitioned Register Banks''. In Proceedings of the 2000 IEEE International Parallel and Distributed Processing Symposium, Cancun, Mexico, May 1-4, 2000.
  23. M.J. Bedy, S. Carr, X. Huang and C.-K. Shene. ``A Visualization System for Multithreaded Programming'', In Proceedings of the 31st ACM SIGCSE Technical Symposium on Computer Science Education, Austin, TX, March 8-12, 2000.
  24. M.J. Bedy, S. Carr, X. Huang and C.-K. Shene. ``The Design and Construction of a User-Level Kernel for Teaching Multithreaded Programming'', In Proceedings of the 1999 ASEE/IEEE Frontiers in Education, San Juan, Puerto Rico, November 10-13, 1999.
  25. S. Jang, S. Carr, P. Sweany, and D. Kuras, ``A Code Generation Framework for VLIW Architectures with Partitioned Register Files''. In Proceedings of the Third International Conference on Massively Parallel Computing Systems, Colorado Springs, Colorado, April 1998.
  26. D. Kuras, S. Carr and P. Sweany. ``Value Cloning for Architectures with Partitioned Register Banks'', In The 1998 Workshop on Compiler Support for Embedded Systems (CASES98), Washington D.C., December 1998.
  27. S. Carr and P. Sweany. ``Improving Software Pipelining with Hardware Support for Self-Spatial Loads'', In Proceedings of the Third Workshop on Interaction between Compilers and Computer Architecture (INTERACT-3), San Jose, CA, October 1998.
  28. S. Carr and Y. Guan. ``Unroll-and-Jam Using Uniformly Generated Sets'', In Proceedings of the 30th IEEE International Symposium on Microarchitecture (MICRO-30), Research Triangle Park NC, December 1997.
  29. C. Ding, S. Carr, and P. Sweany. ``Modulo Scheduling with Cache-Reuse Information'', Lecture Notes in Computer Science 1300, Springer-Verlag, Proceedings of Europar 97, Passau, Germany, August 1997.
  30. S. Carr. ``Combining Optimization for Cache and Instruction-Level Parallelism'', In Proceedings of the 1996 IEEE International Conference on Parallel Architectures and Compiler Techniques (PACT 96), Boston MA, October 1996.
  31. S. Carr, C. Ding and P. Sweany, ``Improving Software Pipelining with Unroll-and-Jam'', In Proceedings of the Twenty-Ninth Annual Hawaii International Conference on System Sciences, Maui HI, January 1996, pp. 183-192.
  32. T. Brasier, P. Sweany, S. Beaty and S. Carr, ``CRAIG: A Practical Framework for Combining Instruction Scheduling and Register Assignment'', In Proceedings of the 1995 IEEE International Conference on Parallel Architectures and Compilation Techniques (PACT 95), Cyprus, June 1995.
  33. S. Carr and R.B. Lehoucq, ``A Compiler Blockable Algorithm for QR Decomposition'', In Proceedings of the 7th SIAM Conference on Parallel Processing for Scientific Computing, San Francisco CA, February 1995.
  34. S. Carr, K.S. McKinley and C-W. Tseng, ``Compiler Optimizations for Improving Data Locality'', In Proceedings of the Sixth ACM International Conference on Architectural Support for Programming Languages and Compilers (ASPLOS-VI), San Jose CA, October 1994.
  35. S. Carr and K. Kennedy, ``Compiler Blockability of Numerical Algorithms'', In Proceedings of Supercomputing '92', Minneapolis MN, November 1992.
  36. S. Carr and K. Kennedy, ``Compiling Scientific Code for Complex Memory Hierarchies'', In Proceedings of the Twenty-Fourth Annual Hawaii International Conference on System Sciences, Kauai HI, January 1991.
  37. S. Carr, D. Callahan and K. Kennedy, ``Improving Register Allocation for Subscripted Variables'', In Proceedings of the ACM SIGPLAN 1990 Conference on Programming Language Design and Implementation (PLDI 90), White Plains NY, June 1990.
  38. S. Carr and K. Kennedy, ``Blocking Linear Algebra Codes for Memory Hierarchies'', In Proceedings of the Fourth SIAM Conference on Parallel Processing for Scientific Computing, Chicago IL, December 1989.
     
Ph.D. Thesis
     
  1.   S. Carr. Memory Hierarchy Management, PhD Thesis, Rice University, September 1992.
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